DIVA: A Dynamic Approach to Microprocessor Verification

Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper, we introduce dynamic veri cation, a novel microarchitectural technique that can signi cantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. The functional checker veri es the correctness of the core processor's computation, permitting only correct results to commit. In the event of an incorrect result, the checker xes the error and ushes any incorrect results from the core using the existing speculation recovery mechanism. Overall design costs can be dramatically reduced because designers need only verify the correctness of the checker unit. The core processor need not be fully correct, only suÆciently correct that its errors do not adversely a ect performance. We detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core processor performance. To make the case for reduced veri cation costs, we argue that the DIVA checker should lend itself to functional and electrical veri cation better than a complex core processor. Finally, future applications of dynamic veri cation are suggested.